1. Field of the Invention
The present invention relates to a back annotation apparatus and method thereof, and more particularly, to an apparatus and a method thereof for carrying out a simulation based on the extraction result in regard to extracted parasitic elements.
2. Description of the Background Art
As processing technologies have progressed and electronic elements have become faster it has become important to eliminate wiring delays. Therefore, after layout is completed, parasitic elements which cause wiring delays are extracted from the layout and, then, a circuit simulation is carried out by using a circuit configuration of the layout and the information of the above described parasitic elements. This is called a back annotation.
In a conventional back annotation flow, a net list with parasitic elements including parasitic element information about all the devices existing within the target layout pattern data and designated nodes is used to carry out a post layout simulation.
Semiconductor integrated circuits, however, have become large scaled in recent years. Accordingly, the time required for parasitic element extraction and post layout simulation becomes large for carrying out a post layout simulation with all of the devices of a semiconductor integrated circuit as targets and, therefore, in many cases implementation in real time is difficult. In addition, work for selecting target nodes of parasitic element extraction within the target layout pattern data have been carried out manually, and therefore has been difficult. Moreover, there is a problem that the more the number of extraction target nodes are, the more difficult the post layout simulation becomes.